Data distribution system

ABSTRACT

A transfer apparatus receives, from a controller, a bit string including a plurality of individual data addressed to plural input/output units. The bit string is divided into data fragments. The data fragments are specified as corresponding to a target input/output unit. The specified data fragment is processed without performing a bit shift operation, and transmitted to the target input/output unit as a target data fragment. The input/output unit receives and stores template information that indicates an area within the target data fragment where the individual data is stored. The individual data is extracted from the target data fragment based on the template information.

TECHNICAL FIELD

The present invention relates to a data distribution system used in afield of control.

BACKGROUND ART

In the field of control, data distribution systems in which onecontroller controls a plurality of input/output units, arranged atpositions away from the controller by several to several hundreds ofmeters, via a network have been widely put into practical use.Conventionally, the number of inputs and outputs per input/output unit(one unit is equal to one bit) ranges from 8 to 64. However, based onuser demands, the number of inputs and outputs per input/output unitranges from 1 to 8, in some recent input/output units. The network to beused is referred to as a field network for the former case, and as asensor/actuator network for the latter case, due to the background ofestablishment in the market and a difference in the number of inputs andoutputs of the input/output units. The technical standards for the fieldnetwork and the sensor/actuator network have been published bygovernment organizations and private organizations (Non-patentLiteratures 1 to 6).

The outline of a conventional data distribution system will be explainedwith reference to FIGS. 1 to 13. In the specification, a network inwhich the number of inputs and outputs of the input/output unit is 8 ormore is referred to as the field network, and a network in which thenumber of inputs and outputs of the input/output unit is less than 8 isreferred to as the sensor/actuator network.

In the data distribution system used in the field of control, thecontroller controls the input/output information of several tens toseveral thousands inputs/outputs via the field network or thesensor/actuator network. That is, the controller monitors the inputstate of an input unit and controls the output state of an output unit.Therefore, as shown in FIG. 1, recent networks have been madehierarchical such that the inputs of from several hundreds to severalthousands are divided into small groups of inputs of several tens, anddata transmission within each group is performed via the sensor/actuatornetwork.

FIG. 1 is a conceptual diagram when the field network and thesensor/actuator network are hierarchical. In FIG. 1, a controller 110 isconnected to a field network 111 having a length of from several tens toseveral thousands of meters, and m groups (m=1 to N) are connected tothe field network 111. A transfer apparatus 121 m connected to the fieldnetwork 111 is arranged in the group m. A plurality of input/outputunits 122 . . . are connected to the transfer apparatus 121 via asensor/actuator network 112 having a length of from several to severalhundreds of meters. That is, the transfer apparatus 121 transmits to thecontroller 110, input state data received from the input/output units122 . . . belonging to its own group, and also distributes control datareceived from the controller 110 to the input/output units 122 . . . ofits own group.

FIG. 2 is a diagram for explaining data distribution to the input/outputunits performed in one group shown in FIG. 1. FIG. 2 depicts a case thatthe controller 110 transmits onto the field network 111, a transmissionframe 123 m addressed to group m, for controlling the output state ofthe input/output unit 122 mn in the group m, and the transfer apparatus121 m in the group m creates a transmission frame 123 mn addressed tothe input/output unit 122 mn from the transmission frame 123 m receivedfrom the field network 111, to transmit the data to the sensor/actuatornetwork 112.

The transmission frame 123 m is a bit string including a header field71, a data field 72, and a check field 73. The transmission frame 123 mnis a bit string including a header field 75, a data field 76, and acheck field 77. The configuration of such a transmission frame isgenerally used in a serial communication, and the similar configurationis used in the Non-patent Literatures 1 to 6. The correspondence betweenthe bit arrangement in the data field and the input/output ports of theinput/output units is determined fixedly such that the least significantbit (LSB) represents the state of the 0-th input/output port.

The unit in the data field in the transmission frame specified in theNon-patent Literatures 1, 2, and 5 is 1 byte. The unit in the data fieldin the transmission frame specified in the Non-patent Literature 4 is 4or 2 bytes. The unit in the data field in the transmission framespecified in the Non-patent Literature 3 is 0.5 byte (4 bits are fixed).The unit in the data field in the transmission frame specified in theNon-patent Literature 6 is 0.5 byte, 1 byte, or 2 bytes.

In FIG. 2, therefore, it is assumed that in the transmission frame 123 mto be transmitted to the field network 111 by the controller 110, theunit in the data field 72 is 1 byte. Further, it is assumed that in thetransmission frame 123 mn to be transmitted to the sensor/actuatornetwork 112 by the transfer apparatus 121 m, the unit in the data field76 is 1 byte. The one-to-one correspondence between the bit position inthe data field and the input/output port is determined fixedly.

That is, the data field 72 in the transmission frame 123 m includes 2×Nbits (N is a multiple of 4), the first bit on the header field 71 sideis the least significant bit (LSB), and the last bit on the check field73 side is the most significant bit (MSB). In FIG. 2, it is shown thatthe input/output unit 122 mn has two output ports mnP0 and mnP1, andhence, 2 bit data addressed to the respective input/output units 122 mnis stored in the data field 72. In other words, the first and the secondbits are data addressed to an input/output unit 122 m 1, and the thirdbit and the fourth bit are data addressed to an input/output unit 122 m2.

In the transmission frame 123 mn, the data field 76 includes 8 bits, thefirst bit b0 on the header field 75 side is the least significant bit(LSB), and the eighth bit b7 on the check field 77 side is the mostsignificant bit (MSB).

The transfer apparatus 121 m receives the transmission frame 123 m, andfetches the (2×(m−1)+1)th bit to the (2×m)th bit in the data field 72 ofthe transmission frame 123 m, in order to create the transmission frame123 mn, and stores these data in bits b0 to b1 in the data field 76 ofthe transmission frame 123 mn, and stores “0” in bits b2 to b7. That is,in the depicted example, “00000001” is stored in the data field 76.

The input/output unit 122 mn extracts the data field 76 from thetransmission frame 123 mn that is fetched from the sensor/actuatornetwork 112, to determine the ON/OFF state of an output port mnPk(k=0, 1) according to the logical state of the first bit b0 and thesecond bit b1 in the data field 76. That is, in an output port mnP0,when b0=“1”, the output state is set to ON, and when b0=“0”, the outputstate is set to OFF. Likewise, in an output port mnP1, when b1=“1”, theoutput state is set to ON, and when b1=“0”, the output state is set toOFF. In the example shown in FIG. 2, since b0=“1” and b1=“0”, the outputstate of the output port mnP0 is ON, and the output state of the outputport mnP1 is OFF.

The processing content in which the transfer apparatus 121 m creates thetransmission frame 123 mn addressed to the input/output unit 122 mn fromthe transmission frame 123 m will be specifically explained withreference to FIGS. 3 and 4.

FIG. 3 illustrates a process in which the transfer apparatus 121 m usesan 8-bit microcomputer to create the transmission frame 123 mn to bedistributed to an input/output unit 122 m 8 having a station number n,from the transmission frame 123 m. FIG. 4 is a diagram for explainingthe processing content related to part “a” shown in FIG. 3.

In FIG. 3, the transfer apparatus 121 m defines constants and variables,and after initializing the variables, obtains the value in the datafield 72 in the transmission frame 123 m according to a functionget_field_network_data( ). The transfer apparatus 121 m then stores d123m[1] from an array variable d123 m, which is data addressed to stationnumber 8, in a variable d123 mn based on station number n=8. Thetransfer apparatus 121 m then shifts the variable d123 mn rightward (ina direction toward the LSB) by 6 bits, which is the number of bitsobtained by multiplying 2 by 3, which is a surplus obtained by dividing“8-1” by 4, so that data addressed to the input/output unit 122 m 8 isstored in order of from the LSB of the variable d123 mn. Lastly, ANDoperation of the variable d123 mn and 0×03 (hexadecimal) is performed inorder to set 0 into the bits storing no data. Thus, generation of datad123 mn is complete, and the data d123 mn is transmitted according to afunction send_sensor_actuator_network( ).

In FIG. 4, the processing in part “a” shown in FIG. 3 is shown in column(A), a processing operation actually performed by a microcomputer isshown in column (B), and the required number of clocks is shown incolumn (C). As shown in column (C), as for the number of clocks requiredwhen the microcomputer executes a command, if one clock is required forone command, in the case of station number n=8, a total of 45 clocks arerequired for the processing for 4 lines in the part “a” shown in FIG. 3,and 33 clocks are required for the bit shift processing.

A process in which the input/output unit 122 m 8 determines an outputstate mnPk from the transmission frame 123 mn will be explainedspecifically with reference to FIGS. 5 to 7. FIGS. 5 and 6 illustrate acase that the input/output unit 122 m 8 uses an 8-bit microcomputer todetermine the output state mnPk from the transmission frame 123 mn. FIG.5 depicts an example in which an output port has the same address, andFIG. 6 depicts an example in which the output port has a differentaddress. FIG. 7 depicts details of the processing content relating topart “b” shown in FIG. 6.

In FIGS. 5 and 6, the input/output unit 122 m 8 defines a constant in aconstant defining section, declares variables in a variable definingsection, and then obtains the value in the data field 76 in thetransmission frame 123 mn according to a functionget_sensor_actuator_network_data( ) into a variable d123 mn. Based onthe value of the low-order 2 bits in the variable d123 mn, when thevalue is 1, the output state of the output port mnPk is turned ON, andwhen the value is 0, the output state of the output port mnPk is turnedOFF.

In FIG. 7, the processing in part “b” shown in FIG. 6 is shown in column(A), a processing operation actually performed by a microcomputer isshown in column (B), and the required number of clocks is shown incolumn (C). As shown in column (C), as for the number of clocks requiredwhen the microcomputer executes a command, if one clock is required forone command, a total of 12 clocks are required for the processing forthe 2 lines in part “b” shown in FIG. 6.

FIG. 8 is a diagram for explaining the configuration of a conventionalhierarchical data distribution system and contents of the processprocedure of the transfer apparatus. FIG. 8 illustrates a case in whichthe controller 110, which controls the whole system, performs settingcontrol of a state quantity output to an object to be controlled, tothree input/output units 250 q (q=A, B, C) via a transfer apparatus 211.As described above, the transfer apparatus 211 is connected to thecontroller 110 via the field network 111, and to the input/output units250 q via the sensor/actuator network 112. The configuration and thecontents of the process procedure of the input/output units 250 q shownin FIG. 8 are shown in FIGS. 9 to 11.

In FIG. 8, the transfer apparatus 211 includes a receiver 221, adividing unit 222, a reception buffer 223, a specifying unit 224, anoperation unit 225, and a transmitter 226. Upon receiving a transmissionframe transmitted by the controller 110 via the field network 111, thereceiver 221 extracts a bit string 113 including a data field, andprovides the bit string to the dividing unit 222.

In FIG. 8, the bit string 113 includes 16 bits. The positions of the LSBand the MSB in the bit string 113 are displayed in the oppositedirection to those shown in FIG. 2. In the bit string 113, the first andthe second bits on the lowest order side indicate data 141A transmittedto the input/output unit 250 q (q=A). The third to the sixth bitsindicate data 141B transmitted to the input/output unit 250 q (q=B). Theseventh to the tenth bits indicate data 141C transmitted to theinput/output unit 250 q (q=C). The eleventh to the sixteenth bits, ofwhich the sixteenth bit is the most significant bit, are not used.

The dividing unit 222 divides the bit string 113 received from thereceiver 221 into data having a 1-byte length, and provides the data tothe reception buffer 223 to store the data. In FIG. 8, since the bitstring 113 includes 16 bits, the bit string 113 is divided into two, andhence, the reception buffer 223 stores a low-order data fragment 231 aand a high-order data fragment 231 b.

The specifying unit 224 specifies data 141 q to be transmitted to theinput/output unit 250 q, based on the low-order data fragment 231 a andthe high-order data fragment 231 b stored in the reception buffer 223,and a station number q (q=A, B, C), and extracts a data fragment of 1byte from the reception buffer 223, to provide it to the operation unit225. In FIG. 8, four one-byte data fragments 131A, 131B, 131Cb, and131Ca are extracted. The data fragment 131A includes the data 141A. Thedata fragment 131B includes the data 141B. The data fragment 131Caincludes low-order two bits of the data 141C, and the data fragment131Cb includes high-order two bits of the data 141C.

The operation unit 225 generates a data fragment 132 q to be sent to theinput/output unit 250 q, from a data fragment 131 q extracted by thespecifying unit 224. In FIG. 8, the operation unit 225 includes an ANDcircuit 225 a to which the data fragment 131A is input, a shift register225 b to which the data fragment 131B is input, an AND circuit 225 c towhich the processing result by the shift register 225 b is input, ashift register 225 d to which the data fragment 131Ca is input, a shiftregister 225 e to which the data fragment 131Cb is input, an OR circuit225 f to which the processing results by the shift registers 225 d and225 e are input, and an AND circuit 225 g to which the processing resultby the OR circuit 225 f is input.

The transmitter 226 stores the data fragment 132 q generated by theoperation unit 225 in a bit string 114 q including a data field in thetransmission frame, and transmits the bit string 114 q to thesensor/actuator network 112.

As shown in FIGS. 9 to 11, the input/output unit 250 q includes areceiver 251 q, a data fragment storage unit 252 q, and a comparator 253qr (r=0 to 3). Upon reception of the transmission frame transmitted bythe transfer apparatus 211 via the sensor/actuator network 112, thereceiver 251 q extracts the bit string 114 q including the data fieldtherefrom, so that the bit string 114 q is stored in the data fragmentstorage unit 252 q. When the (r+1)th bit in the data stored in the datafragment storage unit 252 q is “0”, the comparator 253 qr sets an outputstate 254 qr to OFF, and when the (r+1)th bit is “1”, sets the outputstate 254 qr to ON.

The operation of the conventional data distribution system configured asdescribed above will be explained below. In FIG. 8, the controller 110sets a data field storing a bit string 113 (“1111111101010101” in thedepicted example) including the data 141A (“01” in the depicted example)of two bits addressed to an input/output unit 250A, the data 141B(“0101” in the depicted example) of four bits addressed to aninput/output unit 250B, and the data 141C (“1101” in the depictedexample) of four bits addressed to an input/output unit 250C, in atransmission frame, and transmits the bit string 113 to the transferapparatus 211 via the field network 111.

In the transfer apparatus 211, the receiver 221 extracts the bit string113 including the data field. The extracted bit string 113 is divided bythe dividing unit 222 into the low-order data fragment 231 a includingthe low-order bytes “01010101” and the high-order data fragment 231 bincluding the high-order bytes “11111111”, and both data fragments arestored in the reception buffer 223.

The low-order data fragment 231 a stored in the reception buffer 223includes the data 141A (“01”) to be transferred to the input/output unit250A, the data 141B (“0101”) to be transferred to the input/output unit250B, and half of the data 141C (low-order 2 bits “01”) to betransferred to the input/output unit 250C, and the high-order datafragment 231 b includes the remaining half of the data 141C (high-order2 bits “11”) to be transferred to the input/output unit 250C.

Therefore, the specifying unit 224 creates the data fragment 131A byadding a station number A to the low-order data fragment 231 a in whichthe data 141A to be transferred to the input/output unit 250A is stored,and sends the data fragment 131A to the operation unit 225. Further, thespecifying unit 224 creates the data fragment 131B by adding a stationnumber B to the low-order data fragment 231 a in which the data 141B tobe transferred to the input/output unit 250B is stored, and sends thedata fragment 131B to the operation unit 225. Since the data 141C to betransferred to the input/output unit 250C is included in the low-orderdata fragment 231 a and the high-order data fragment 231 b, thespecifying unit 224 creates the data fragments 131Ca and 131Cb by addinga station number C to the low-order data fragment 231 a and thehigh-order data fragment 231 b, and sends the data fragments to theoperation unit 225.

When all the data 141 q addressed to the input/output unit 250 q isincluded in one data fragment 131 q, the operation unit 225 performsshift operation with respect to the data fragment 131 q so that the data141 q is stored in order from the LSB of the data fragment 132 q, andperforms AND operation with respect to the data fragment 131 q so thatbits other than the data 141 q are set to “0”, to create the datafragment 132 q to be sent to the transmitter 226.

On the other hand, when the data 141 q is divided into two datafragments 131 qa and 131 qb, the data 141 q is extracted from the datafragments 131 qa and 131 qb, to generate the data fragment 132 q byperforming the shift operation and OR operation so that the data 141 qis stored in order of from the LSB of the data fragment 132 q, to sendthe data fragment 132 q to the transmitter 226, after setting bits otherthan the data 141 q to “0”.

In other words, all the data 141A (“01”) addressed to the input/outputunit 250A is included in the data fragment 131A (“01010101”) output bythe specifying unit 224. Therefore, the operation unit 225 can determinefrom the station number A that the low-order 2 bits need only to beextracted from the data fragment 131A. In order to set the bits otherthan the data 141A to “0”, AND operation of the data fragment 131A(“01010101”) and a constant “00000011” is performed by the AND circuit225 a, and the obtained data “0000001” is sent to the transmitter 226 asa data fragment 132A. The transmitter 226 creates a transmission framehaving a data field in which the data fragment 132A includes a bitstring 114A, and transmits the transmission frame to the input/outputunit 250A.

In the input/output unit 250A, a data fragment storage unit 252A storesthe bit string 114A (“0000001”) extracted from the data field in thetransmission frame received by a receiver 251A. A comparator 253A0performs AND operation of the data “00000001” stored in the datafragment storage unit 252A and a constant “00000001”, and since theoperation result is not “0”, sets an output 254A0 to ON. A comparator253A1 performs AND operation of the data “00000001” stored in the datafragment storage unit 252A and a constant “00000010”, and since theoperation result is “0”, sets an output 254A1 to OFF.

Further, in the operation unit 225, the data 141B (“0101”) addressed tothe input/output unit 250B is included in the data fragment 131B(“01010101”) output by the specifying unit 224. Therefore, the operationunit 225 can determine from the station number B that the third to thesixth bits in the data fragment 131B need only to be extracted. In orderto justify the bit position to the right end, the operation unit 225provides the data fragment 131B to the shift register 225 b, to shiftthe data bit rightward by 2 bits, to generate a data fragment 131B0(“00010101”). In order to set bits other than the data 141B to “0”, ANDoperation of the data fragment 131B0 (“00010101”) and a constant“00001111” is performed by the AND circuit 225 c, and the obtained data“0000101” is sent to the transmitter 226 as a data fragment 132B. Thetransmitter 226 creates a transmission frame having a data field inwhich the data fragment 132B includes a bit string 114B, and transmitsthe transmission frame to the input/output unit 250B.

In the input/output unit 250B, a data fragment storage unit 252B storesthe bit string 114B (“00000101”) extracted from the data field in thetransmission frame received by a receiver 251B. A comparator 253B0performs AND operation of the data “00000101” stored in the datafragment storage unit 252B and the constant “00000001”, and since theoperation result is not “0”, sets an output 254B0 to ON. A comparator253B1 performs AND operation of the data “00000101” stored in the datafragment storage unit 252B and the constant “00000010”, and since theoperation result is “0”, sets an output 254B1 to OFF.

A comparator 253B2 performs AND operation of the data “00000101” storedin the data piece storage unit 252B and a constant “00000100”, and sincethe operation result is not “0”, sets an output 254B2 to ON. Acomparator 253B3 performs AND operation of the data “00000101” stored inthe data piece storage unit 252B and a constant “00001000”, and sincethe operation result is “0”, sets an output 254B3 to OFF.

On the other hand, the data 141C (“1101”) addressed to the input/outputunit 250C is divided into two, and included in the data fragment 131Ca(“01010101”) and the data fragment 131Cb (“11111111”) output by thespecifying unit 224. Therefore, the operation unit 225 can determinefrom the station number C that the high-order 2 bits need only to beextracted from the data fragment 131Ca and the low-order 2 bits needonly to be extracted from the data fragment 131Cb. In order to justifythe bit position to the right end, the operation unit 225 provides thedata fragment 131Ca to the shift register 225 d, to shift the data bitrightward by 6 bits, to generate a data fragment 131C0 (“00000001”).

Further, as for the data fragment 131Cb, in order to justify the bitposition at the right end to the position of the third bit, theoperation unit 225 provides the data fragment 131Cb to the shiftregister 225 e, to shift the data bit leftward by 2 bits, to generate adata fragment 131C1 (“11111100”). To store the data fragment 131C0 andthe data fragment 131C1 in a 1-byte data fragment, OR operation of thedata fragment 131C0 and the data fragment 131C1 is performed by an ORcircuit 225 f, to generate a data fragment 131C2 (“11111101”). In orderto set the bits other than the data 141C (“1101”) to “0”, AND operationof the data fragment 131C2 (“11111101”) and a constant “00001111” isperformed by the AND circuit 225 g, and the result is sent to thetransmitter 226 as a data fragment 132C (“0001101”). The transmitter 226creates a transmission frame having a data field in which the datafragment 132C includes a bit string 114C, and transmits the transmissionframe to the input/output unit 250C.

In the input/output unit 250C, a data fragment storage unit 252C storesthe bit string 114C (“00001101”) extracted from the data field in thetransmission frame received by a receiver 251C. A comparator 253C0performs AND operation of the data “00001101” stored in the datafragment storage unit 252C and the constant “00000001”, and since theoperation result is not “0”, sets an output 254C0 to ON. A comparator253C1 performs AND operation of the data “00001101” stored in the datafragment storage unit 252C and the constant “00000010”, and since theoperation result is “0”, sets an output 254C1 to OFF.

A comparator 253C2 performs AND operation of the data “00001101” storedin the data fragment storage unit 252C and the constant “00000100”, andsince the operation result is not “0”, sets an output 254C2 to ON. Acomparator 253C3 performs AND operation of the data “00001101” stored inthe data fragment storage unit 252C and the constant “00001000”, andsince the operation result is not “0”, sets an output 254C3 to ON.

With reference to FIGS. 12 and 13, a process in which the transferapparatus 211 creates the data fragment 132 q (q=A to C) from the bitstring 113 will be specifically explained. FIG. 12 illustrates a case inwhich the transfer apparatus 211 uses an 8-bit microcomputer to executethe processing. FIG. 13 is a diagram for explaining the details of theprocess related to part “c” shown in FIG. 12. In FIG. 13, the process inpart “c” shown in FIG. 12 is shown in column (A), a processing operationactually performed by the microcomputer is shown in column (B), and therequired number of clocks is shown in column (C). As shown in column(C), as for the number of clocks required when the microcomputerexecutes a command, if one clock is required for one command, a total of99 clocks are required for the process in part “c” shown in FIG. 12.

The Non-patent Literatures mentioned above are as follows:

Non-patent Literature 1: JISB3511 Standard OPCN-1 (Standard for thefield network published from a government organization).

Non-patent Literature 2: EN50170 Standard PROFIBUS (Standard for thefield network published from a government organization).

Non-patent Literature 3: IEC62026-2 Standard AS-interface (Standard forthe sensor/actuator network published from a government organization).

Non-patent literature 4: CC-Link by CC-Link Association (Standard forthe field network published from a private organization).

Non-patent Literature 5: DeviceNet by ODVA (Standard for the fieldnetwork published from a private organization).

Non-patent Literature 6: CC-Link/LT by CC-Link Association (Standard forthe sensor/actuator network published from the private organization).

However, according to the conventional processing method, a bit shiftoperation is required when the transfer apparatus transfers data to theinput/output unit, thereby causing a problem in that it takes time toperform processing for creating a transmission frame addressed to theinput/output unit.

The time required until the transfer apparatus finishes processing fordistributing data to all input/output units through the sensor/actuatornetwork is calculated by multiplying the processing time for one unit bythe number of input/output units. Therefore, there is a problem in thata delay in the processing due to the shift process causes performancedeterioration in the distribution processing.

The present invention has been achieved in order to solve the aboveproblems. It is an object of the present invention to provide a datadistribution system, which does not require the bit shift operation bythe transfer apparatus.

DISCLOSURE OF THE INVENTION

According to the present invention, a data distribution system includesa controller that transmits a bit string including a plurality ofindividual data, a transfer apparatus that receives the bit string fromthe controller, extracts the individual data from the bit stringreceived, and transfers the individual data to correspondinginput/output units, and a plurality of input/output units, each of whichcontrols an input/output state based on the individual data receivedfrom the transfer apparatus. The transfer apparatus includes a dividingunit that divides the bit string received from the controller, into datafragments having a size easy to handle, a specifying unit thatspecifies, from the data fragments, a data fragment that includes theindividual data addressed to a target input/output unit, an operatingunit that processes the specified data fragment without performing a bitshift operation, generates one target data fragment for each of theinput/output units, and transmits the target data fragment to therespective input/output units, and a transmitting unit that transmitstemplate information to the respective input/output units, where thetemplate information indicates an area where the individual datarelative to the corresponding input/output unit is stored in the targetdata fragment. The input/output unit includes a storing unit that storesthe template information received from the transfer apparatus, and anextracting unit that extracts the individual data used by theinput/output unit from the target data fragment received from thetransfer apparatus, based on the template information stored.

According to the present invention, because the bit shift operation bythe transfer apparatus is not required, a data fragment to betransmitted to the input/output unit can be generated in short time.Therefore, it is possible to improve the processing efficiency of theprocess in which one controller distributes individual data to aplurality of input/output units.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual diagram of a field network and a sensor/actuatornetwork that are hierarchical;

FIG. 2 is a diagram for explaining data distribution to input/outputunits performed in one group shown in FIG. 1;

FIG. 3 is a diagram for specifically explaining a process in which atransfer apparatus shown in FIG. 2 creates a transmission frameaddressed to the input/output units in the group based on a transmissionframe received from a controller;

FIG. 4 is a diagram for explaining details of the process related topart “a” shown in FIG. 3;

FIG. 5 is a diagram for specifically explaining the process in which theinput/output unit shown in FIG. 2 determines an output state from thetransmission frame received from the transfer apparatus (when an outputport has the same address);

FIG. 6 is a diagram for specifically explaining the process in which theinput/output unit shown in FIG. 2 determines an output state from thetransmission frame received from the transfer apparatus (when the outputport has a different address);

FIG. 7 is a diagram for explaining details of the process related topart “b” shown in FIG. 6;

FIG. 8 is a diagram for explaining a configuration of a conventionalhierarchical data distribution system and a process executed by atransfer apparatus;

FIG. 9 is a diagram for explaining a configuration and a processexecuted by an input/output unit in the conventional data distributionsystem shown in FIG. 8;

FIG. 10 is a diagram for explaining a configuration and a processexecuted by another input/output unit in the conventional datadistribution system shown in FIG. 8;

FIG. 11 is a diagram for explaining a configuration and a processexecuted by still another input/output unit in the conventional datadistribution system shown in FIG. 8;

FIG. 12 is a diagram for specifically explaining a process in which thetransfer apparatus shown in FIG. 8 creates a data fragment to betransmitted to the respective input/output units based on a bit stringreceived from the controller;

FIG. 13 is a diagram for explaining details of the process related topart “c” shown in FIG. 12;

FIG. 14 is a diagram for explaining a configuration of a datadistribution system and a process executed by a transfer apparatusaccording to one embodiment of the present invention;

FIG. 15 is a diagram for explaining the configuration and the processexecuted by an input/output unit shown in FIG. 14;

FIG. 16 is a diagram for explaining the configuration and the processexecuted by another input/output unit shown in FIG. 14;

FIG. 17 is a diagram for explaining the configuration and the processexecuted by still another input/output unit shown in FIG. 14;

FIG. 18 is a diagram for specifically explaining a process in which thetransfer apparatus shown in FIG. 14 creates a data fragment to betransmitted to the respective input/output units based on a bit stringreceived from the controller;

FIG. 19 is a diagram for explaining details of the process related topart “d” shown in FIG. 18;

FIG. 20 is a diagram for specifically explaining a process in which theinput/output unit shown in FIG. 14 determines an input/output statebased on the bit string received from the transfer apparatus; and

FIG. 21 is a diagram for explaining details of the process related topart “e” shown in FIG. 20.

BEST MODE FOR CARRYING OUT THE INVENTION

Exemplary embodiments of a data collection system according to thepresent invention will be explained in detail with reference to theaccompanying drawings.

FIG. 14 is a diagram for explaining a configuration of a datadistribution system and a process executed by a transfer apparatusaccording to one embodiment of the present invention. FIG. 14illustrates a case in which a controller 10 that controls the wholesystem performs setting control of output state of an object to becontrolled, with respect to three input/output units 50 q (q=A, B, C)via a transfer apparatus 20. The transfer apparatus 20 is connected tothe controller 10 via a field network 12, and to the input/output units50 q via a sensor/actuator network 17. The configuration and theprocessing content of the input/output units 50 q are shown in FIGS. 15to 17.

The transfer apparatus 20 includes a receiver 21, a dividing unit 22, areception buffer 23, a specifying unit 24, an operation unit 25, and atransmitter 26. Upon receiving a transmission frame transmitted by thecontroller 10 via the field network 12, the receiver 21 extracts a bitstring 13 including a data field, and provides the bit string to thedividing unit 22.

In FIG. 14, the bit string 13 includes 16 bits. The position of the LSBin the bit string 13 is at the right end, and the position of the MSB isat the left end. In the bit string 13, the first and the second bits onthe lowest order side indicate data 41A, the third to the sixth bitsindicate data 41B, the seventh to the tenth bits indicate data 41C, andthe eleventh to the sixteenth bits, of which the sixteenth bit is themost significant bit, are not used. Data 41 q is data to be transmittedto the input/output unit 50 q.

The dividing unit 22 divides the bit string 13 received from thereceiver 21 into data having a 1-byte length, and provides the data tothe reception buffer 23 to store the data. In FIG. 14, since the bitstring 13 includes 16 bits, the bit string 13 is divided into two, andhence, the reception buffer 23 stores a low-order data fragment 23 a anda high-order data fragment 23 b.

The specifying unit 24 specifies data 41 q to be transmitted to theinput/output unit 50 q, based on the low-order data fragment 23 a andthe high-order data fragment 23 b stored in the reception buffer 23, anda station number q (q=A, B, C), and extracts a data fragment of 1 bytefrom the reception buffer 23, to provide it to the operation unit 25. InFIG. 14, four one-byte data fragments 31A, 31B, 31C1, and 31C0 areextracted. The data fragment 31A includes the data 41A. The datafragment 31B includes the data 41B. The data fragment 31C1 includeshigh-order two bits of the data 41C, and the data fragment 31C0 includeslow-order two bits of the data 41C.

The operation unit 25 generates a data fragment 32 q to be sent to theinput/output unit 50 q, from the data fragments 31A, 31B, 31C1, and 31C0extracted by the specifying unit 24. In FIG. 14, the operation unit 25includes an AND circuit 25 b to which the data fragment 31C1 is input,an AND circuit 25 a to which the data fragment 31C0 is input, and an ORcircuit 25 c to which the processing result by the AND circuits 25 b and25 a is input.

The transmitter 26 stores the data fragment 32 q generated by theoperation unit 25 in a bit string 14 q including a data field in thetransmission frame, and transmits the bit string 14 q to thesensor/actuator network 17.

As shown in FIGS. 15 to 17, the input/output unit 50 q includes areceiver 51 q, a data fragment storage unit 52 q, template storage units55 qr (r=0 to 3), and comparators 53 qr (r=0 to 3). Though not shown,template information, including a bit pattern indicating an area inwhich the data 41 q applied to the input/output unit 50 q is stored inthe bit string 14 q to be transmitted by the transfer apparatus 20, isinput to the input/output unit 50 q in one-to-one correspondence withthe comparators 53 qr. In the embodiment, the transfer apparatus 20transfers the template information before starting data distributionprocess to the input/output unit 50 q, such as at the time of startup ofthe system.

Upon reception of the transmission frame transmitted by the transferapparatus 20 onto the sensor/actuator network 17, the receiver 51 qextracts the bit string 14 q including the data field therefrom, so thatthe bit string 14 q is stored in the data fragment storage unit 52 q.The receiver 51 q also allows a template storage unit 52 qr to store thetemplate information received separately from the transfer apparatus 20.The comparator 53 qr performs AND operation of the data fragment 32 qstored by the data fragment storage unit 52 q and the templateinformation stored by the template storage unit 52 qr, and when theresult is “0”, sets an output state 54 qr to OFF, and when the result isnot “0”, sets the output state 54 qr to ON.

The operation of the data distribution system according to theembodiment configured as described above will be explained below. InFIG. 14, the transfer apparatus 20 receives an instruction from thecontroller 10 before starting the data distribution processing to theinput/output unit 50 q, and transmits the template information to therespective input/output units 50 q. As a result, in the input/outputunits 50 q, the template information is stored in the template storageunit 55 qr.

In other words, in input/output unit 50A, template information“00000001” is stored in a template storage unit 55A0, and templateinformation “00000010” is stored in a template storage unit 55A1. Ininput/output unit 50B, template information “00000100” is stored in atemplate storage unit 55B0, template information “00001000” is stored ina template storage unit 55B1, template information “00010000” is storedin a template storage unit 55B2, and template information “00100000” isstored in a template storage unit 55B3. In input/output unit 50C,template information “01000000” is stored in a template storage unit55C0, template information “10000000” is stored in a template storageunit 55C1, template information “00000001” is stored in a templatestorage unit 55C2, and template information “00000010” is stored in atemplate storage unit 55C3.

After the transfer apparatus 20 finishes the preprocessing describedabove, the controller 10 sets in a transmission frame, a data field thatstores the bit string 13 (“1111111101010101” in the depicted example)including the data 41A (“01” in the depicted example) of two bitsaddressed to the input/output unit 50A, the data 41B (“0101” in thedepicted example) of four bits addressed to the input/output unit 50B,and the data 41C (“1101” in the depicted example) of four bits addressedto the input/output unit 50C, and transmits the bit string 13 to thetransfer apparatus 20 via the field network 12.

In the transfer apparatus 20, the receiver 21 extracts the bit string 13including the data field. The extracted bit string 13 is divided by thedividing unit 22 into the low-order data fragment 23 a including thelow-order bytes “01010101” and the high-order data fragment 23 bincluding the high-order bytes “11111111”, and the both data fragmentsare stored in the reception buffer 23.

The low-order data fragment 23 a stored in the reception buffer 23includes the data 41A (“01”) to be transferred to the input/output unit50A, the data 41B (“0101”) to be transferred to the input/output unit50B, and half of the data 41C (low-order 2 bits “01”) to be transferredto the input/output unit 50C, and the high-order data fragment 23 bincludes the remaining half of the data 41C (high-order 2 bits “11”) tobe transferred to the input/output unit 50C.

Therefore, the specifying unit 24 creates the data fragment 31A byadding a station number A to the low-order data fragment 23 a in whichthe data 41A to be transferred to the input/output unit 50A is stored,and sends the data fragment 31A to the operation unit 25. Further, thespecifying unit 24 creates the data fragment 31B by adding a stationnumber B to the low-order data fragment 23 a in which the data 41B to betransferred to the input/output unit 50B is stored, and sends the datafragment 31B to the operation unit 25. Because the data 41C to betransferred to the input/output unit 50C is included in the low-orderdata fragment 23 a and the high-order data fragment 23 b, the specifyingunit 24 creates the data fragments 31C1 and 31C0 by adding a stationnumber C to the low-order data fragment 23 a and the high-order datafragment 23 b, and sends the data fragments to the operation unit 25.

When the entire data 41 q addressed to the input/output unit 50 q isincluded in one data fragment 31 q, the operation unit 25 designates thedata fragment 31 q as the data fragment 32 q to be sent to thetransmitter 26, without performing any special processing. On the otherhand, when the data 41 q is divided into two data fragments 31 q 0 and31 q 1, the operation unit 25 sets bits other than the data 41 q in thedata fragments 31 q 0 and 31 q 1 to “0”, and generates the data fragment32 q to be sent to the transmitter 26, by performing OR operation of thetwo data fragments.

In other words, in the operation unit 25, all of the data 41A (“01”)addressed to the input/output unit 50A is included in the data fragment31A (“01010101”) output by the specifying unit 24. Therefore, theoperation unit 25 sends the data fragment 31A as data fragment 32Adirectly to the transmitter 26. The transmitter 26 creates atransmission frame having a data field in which the data fragment 32Aincludes a bit string 14A, to transmit the transmission frame to theinput/output unit 50A via the sensor/actuator network 17.

In the input/output unit 50A, data fragment storage unit 52A stores thebit string 14A (“01010101”) extracted from the data field in thetransmission frame received by receiver 51A. A comparator 53A0 performsAND operation of the data “01010101” stored in the data fragment storageunit 52A and the template information “00000001” stored in the templatestorage unit 55A0, and since the operation result is not “0”, sets anoutput 54A0 to ON. A comparator 53A1 performs AND operation of the data“01010101” stored in the data fragment storage unit 52A and the templateinformation “00000010” stored in the template storage unit 55A1, andsince the operation result is “0”, sets an output 54A1 to OFF.

Further, in the operation unit 25, all the data 41B (“0101”) addressedto the input/output unit 50B is included in the data fragment 31B(“01010101”) output by the specifying unit 24. Therefore, the operationunit 25 sends the data fragment 31B as data fragment 32B directly to thetransmitter 26. The transmitter 26 creates a transmission frame having adata field in which the data fragment 32B includes a bit string 14B, totransmit the transmission frame to the input/output unit 50B via thesensor/actuator network 17.

In the input/output unit 50B, data fragment storage unit 52B stores thebit string 14B (“01010101”) extracted from the data field in thetransmission frame received by receiver 51B. A comparator 53B0 performsAND operation of the data “01010101” stored in the data fragment storageunit 52B and the template information “00000100” stored in the templatestorage unit 55B0, and since the operation result is not “0”, sets anoutput 54B0 to ON. A comparator 53B1 performs AND operation of the data“01010101” stored in the data fragment storage unit 52B and the templateinformation “00001000” stored in the template storage unit 55B1, andsince the operation result is “0”, sets an output 54B1 to OFF.

A comparator 53B2 performs AND operation of the data “01010101” storedin the data fragment storage unit 52B and the template information“00010000” stored in the template storage unit 55B2, and since theoperation result is not “0”, sets an output 54B2 to ON. A comparator53B3 performs AND operation of the data “01010101” stored in the datafragment storage unit 52B and the template information “00100000” storedin the template storage unit 55B3, and since the operation result is“0”, sets an output 54B3 to OFF.

On the other hand, the data 41C addressed to the input/output unit 50Cis divided into two, and included in the data fragment 31C0 (“01010101”)and the data fragment 31C1 (“11111111”) output by the specifying unit24. Therefore, the operation unit 25 can determine from the stationnumber C that the high-order 2 bits need only to be extracted from thedata fragment 31C0 and the low-order 2 bits need only to be extractedfrom the data fragment 31C1. In order to set bits other than thehigh-order 2 bits to “0” in the data fragment 31C0, the AND circuit 25 aof the operation unit 25 performs AND operation of the data fragment31C0 (“01010101”) and a constant “11000000”, to generate a data fragment31C2 (“01000000”).

For the data fragment 31C1, AND operation of the data fragment 31C1(“11111111”) and a constant “00000011” is performed by the AND circuit25 b in order to set bits other than the low-order 2 bits to “0”, togenerate a data fragment 31C3 (“00000011”). Further, the OR circuit 25 cperforms OR operation of the data fragment 31C2 and the data fragment31C3 to generate a data fragment 32C (“01000011”), and provides the datafragment 32C to the transmitter 26. The transmitter 26 creates atransmission frame having a data field in which the data fragment 32Cincludes a bit string 14C, and transmits the transmission frame to theinput/output unit 50C via the sensor/actuator network 17.

In the input/output unit 50C, data fragment storage unit 52C stores thebit string 14C (“01000011”) extracted from the data field in thetransmission frame received by receiver 51C. A comparator 53C0 performsAND operation of the data “01000011” stored in the data fragment storageunit 52C and the template information “01000000” stored in the templatestorage unit 55C0, and since the operation result is not “0”, sets anoutput 54C0 to ON. A comparator 53C1 performs AND operation of the data“01000011” stored in the data fragment storage unit 52C and the templateinformation “10000000” stored in the template storage unit 55C1, andsince the operation result is “0”, sets an output 54C1 to OFF.

A comparator 53C2 performs AND operation of the data “01000011” storedin the data fragment storage unit 52C and the template information“00000001” stored in the template storage unit 55C2, and since theoperation result is not “0”, sets an output 54C2 to ON. A comparator53C3 performs AND operation of the data “01000011” stored in the datafragment storage unit 52B and the template information “00000010” storedin the template storage unit 55C3, and since the operation result is not“0”, sets an output 54C3 to ON.

The process in which the transfer apparatus 20 creates the data fragment32 q from the bit string 13 will be explained specifically withreference to FIGS. 18 and 19. FIG. 18 illustrates a case in which thetransfer apparatus 20 uses an 8-bit microcomputer to execute theprocess. FIG. 19 is a diagram for explaining details of the processrelated to part “d” shown in FIG. 18.

In the transfer process in FIG. 18, a constant defining unit definesconstants, a variable defining unit declares variables, and a variableinitializing unit defines an initial value of the variables. Next, thevalue of the bit string 13 is stored in a variable d13 according to afunction get_field_network_data( ), to execute the process in order ofdata transmission to the input/output units 50 q in a subsequentfor-loop.

In FIG. 19, the processing in part “d” shown in FIG. 18 is shown incolumn (A), a processing operation actually performed by a microcomputeris shown in column (B), and the required number of clocks is shown incolumn (C). In column (C), the number of clocks required for themicrocomputer to perform the process for one line is expressed as 1, thenumber of clocks for lines that are not executed as a result ofcondition decision is expressed as 0, and the number of clocks for linesto be executed is expressed as 1, and the total of number of clocks 30is shown in the lowermost line.

That is, in the conventional example (FIG. 13), 99 clocks are requiredfor the data transfer process. However, in the embodiment, because thetransfer process can be finished within 30 clocks, it is understood thatthe processing time of the transfer apparatus can be considerablyreduced.

FIGS. 20 and 21 are diagrams for specifically explaining the process inwhich the input/output unit 50 q determines the output state from datastored in the data fragment storage unit 52 q. FIG. 20 illustrates acase that the input/output unit 50 q uses an 8-bit microcomputer toexecute the processing. FIG. 21 illustrates details of the processrelated to part “e” shown in FIG. 20.

In FIG. 20, in the input/output unit, a constant defining unit definesconstants, a variable defining unit declares variables, and after thevariables are assigned values for each of the input/output units, thevalue of the bit string 14 q is fetched, to determine the state of anoutput 54 qk (k=0 to 3).

In FIG. 21, the processing in part “e” shown in FIG. 20 is shown incolumn (A), a processing operation actually performed by a microcomputeris shown in column (B), and the required number of clocks is shown incolumn (C). In column (C), it is seen that 12 clocks are required forexecuting the process in part “e” shown in FIG. 20. For thecorresponding process in the conventional example (FIG. 7), the numberof clocks required for executing the processing is 12 clocks. Thus, inthe present embodiment, the total processing time of the transferapparatus can be considerably reduced, while maintaining the processingtime of the input/output unit.

INDUSTRIAL APPLICABILITY

The present invention is suitable as a data distribution system in whichone controller distributes individual data to a plurality ofinput/output units, and the processing efficiency of which is improved.

1. A data distribution system comprising: a controller that transmits abit string including a plurality of individual data; a transferapparatus that receives the bit string from the controller, extracts theindividual data from the bit string received, and transfers theindividual data to corresponding input/output units; and a plurality ofinput/output units, each of which controls an input/output state basedon the individual data received from the transfer apparatus, wherein thetransfer apparatus includes a dividing unit that divides the bit stringreceived from the controller into data fragments having a size easy tohandle; a specifying unit that specifies, from the data fragments, aspecified data fragment that includes the individual data addressed to atarget input/output unit; an operating unit that processes the specifieddata fragment without performing a bit shift operation, generates atarget data fragment for each of the input/output units, and transmitsthe target data fragment to the respective input/output units through atransmitting unit; and the transmitting unit that transmits the targetdata fragments and template information to the respective input/outputunits, wherein the template information indicates an area where theindividual data relative to the corresponding input/output unit isstored in the target data fragment, and the input/output unit includes astoring unit that stores the template information received from thetransfer apparatus; and an extracting unit that extracts the individualdata used by the input/output unit from the target data fragmentreceived from the transfer apparatus, based on the template informationstored.